By virtue of continued scaling of semiconductor technologies, each generation of technology node has become smaller with more complex circuits than the previous generation. In the course of scaling a device, functional density (i.e., the number of devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling process generally provides benefits by increasing production efficiency and lowering associated costs; however, it can also result in complexities of the manufacturing process including alignment issues, etc.
For example, double patterning lithography (DPL) is generally used in fin field effect transistor (FinFET) fabrication processes. A conventional DPL process uses two mask patterns, a mandrel pattern and a cut pattern that removes unwanted portions of the mandrel pattern, a derivative, or both. For example, the DPL process forms a fin using the mandrel pattern and then cuts the fin into two or more sections using the cut pattern. A conventional fin isolation process uses another patterning process to form an isolation structure between two adjacent fins.
Various issues arise from these conventional processes. For example, formation of fins in different density regions may result in different fin profiles due to loading issues, e.g., density of the fin structures. These profile issues may lead to misalignment of structures, amongst other issues. In more specific examples, fin spacing between adjacent fins may result in different fin profiles, with an isolated side of the fin being more tapered compared to a dense fin side. By way of illustration, if only one (1) fin pitch is close to an isolated fin side (e.g., single fin cut), the taper is not obvious; however, if there are three or more fin pitch spaces close to the isolated fin side (e.g., cutting more than three (3) fins), a taper on the isolated fin side becomes very noticeable.